Memory is utilized in a variety of circuit applications to store desired information. One type of memory, for example, may be configured into different data widths (e.g., depending upon the application or data requirements). For example, a memory may have a maximum memory size of 8,192 bits and be configured with data widths of one bit (i.e., 8,192 by 1), two bits (i.e., 4,096 by 2), four bits (i.e., 2,048 by 4), eight bits (i.e., 1,024 by 8), sixteen bits (i.e., 512 by 16), or thirty two bits (i.e., 256 by 32).
A desired feature for a memory that is configurable into different data widths (e.g., wider data widths) is the ability to write to only a portion of the data width. One technique, known as byte enable logic, allows a specific byte to be written to within a wider data width block. For example, the lower eight bits may be written to instead of the entire thirty-two bit word (e.g., when configured in a 256 by 32 configuration, as in the above example). However, there may exist significant routing congestion around the memory and only a limited number of pins may be available for the memory within an integrated circuit. Consequently, it is not desirable to have dedicated byte enable signal paths to the memory and there may simply be no routing (e.g., pin) resources available to accommodate the byte enable logic signals. As a result, there is a need for improved byte enable logic techniques.